1. Field of the Invention
The present invention relates generally to electronic systems modeling and development and, more specifically, to hardware simulators and emulators.
2. Description of the Related Art
Electronics engineers and others who design electronic systems use simulators and emulators to test their designs for both operability and compatibility with existing systems or components with which they are to interface. A simulator is commonly a general-purpose computer workstation that runs a simulation program. The program models or simulates in software the circuits of the design to be evaluated, simulates application to the circuit of the requisite input signals, and outputs the data representing the resulting output signals that the circuit produces in response to the input signals.
As described in U.S. Pat. No. 5,946,472, issued to IBM Corporation and incorporated into this patent specification in its entirety by this reference, simulators by themselves have been found to be relatively inefficient because the concurrent operations they simulate typically create a bottleneck in terms of processing speed. Concurrent operations are those that model the circuit logic, and typically account for approximately 90% of the available processing load on the workstation; sequential operations, which are those that apply test vector data and otherwise simulate sequentially occurring activities with respect to the simulation, typically account for the remaining approximately 10% of the processing load on the workstation. To help alleviate this bottleneck, accelerator hardware can be interfaced with a workstation. An accelerator is typically an electronic circuit board system that performs the concurrent processing, thereby taking that portion of the load off the workstation. The workstation can then concentrate the majority of its available processing power on sequential operations.
A further improvement in processing efficiency can be gained by providing an emulator or an emulator/accelerator combination. An emulator/accelerator is a large-scale hardware configuration typically implemented in field-programmable gate arrays (FPGAs) or some other type of software-configurable custom hardware. Because the logic is modeled in hardware (e.g., FPGAs) that approaches the same degree of parallel operation that the actual circuit being modeled would exhibit, the emulator/accelerator can perform the concurrent operations much faster than an accelerator alone. The emulator/accelerator is capable of emulating many types of computer system hardware and other logic, including, for example, memory devices. An example of an emulator/accelerator is the ETX produced by IBM Corporation. The ETX executes a logic model embodied in suitable software that reflects a combination of a user model logic portion and non-user-model logic portion. The user model logic portion may be derived from (e.g., compiling) a netlist for the hardware design under test. Accordingly, this portion represents the functionality of the hardware design. The non-user-model logic portion is peripheral to the hardware design itself and is included for the purpose of providing peripheral functions to the emulation, such as high-speed multiplexed data communication between the emulator/accelerator and a host workstation.
The chief advantage of including an emulator/accelerator is that it can perform the concurrent operations in parallel with the sequential operations performed by the workstation to which it is connected. In some cases, an emulator/accelerator can be interfaced to target hardware representing a portion of the system that is being tested or otherwise evaluated. For example, the target hardware may be a personal computer in which the microprocessor has been removed and replaced with a cable connecting it to the emulator/accelerator.
The above referenced patent describes an improved emulator/accelerator system that includes one or more xe2x80x9cbehavior cardsxe2x80x9d for performing the sequential operations, thereby taking that portion of the load off the workstation. The behavior card is quite versatile and can apply test vectors or model sequential devices such as a memory. Thus, the emulator/accelerator performs the concurrent operations while the behavior card performs the sequential operations. The two can operate in parallel. Nevertheless, the two do not operate asynchronously with each other. Rather, they are synchronized with each other and operate in lock-step fashion by means of a handshake. On each cycle of the emulation, the emulator/accelerator produces a xe2x80x9cSTEPxe2x80x9d or xe2x80x9cBEGIN_CYCLExe2x80x9d signal. In response to this signal, the behavior card generates a xe2x80x9cHALTxe2x80x9d signal, which indicates that the behavior card has begun processing data it received from the emulator/accelerator on the previous cycle and needs the emulator/accelerator to wait until it has finished doing so. When it has finished, the behavior card drops the HALT signal. In response to the deassertion of the HALT signal, the emulator/accelerator can reassert the STEP signal when it is ready to begin another emulation cycle. In addition, if the behavior card asserts the HALT signal but detects an error condition, requires more input data before it can continue, or otherwise needs to suspend the emulation, it can assert a xe2x80x9cSTOPPEDxe2x80x9d signal. This signal provides an indication of such a condition to the workstation and to any other behavior cards in the system. While improving the processing time of an embedded simulation environment, there are still improvements that can be made to the processing efficiency, especially when peripherals beyond the behavior card are used. Moreover, in accordance with the present invention it has been recognized that there are circumstances under which processing efficiency can be improved by improving and refining the handshaking protocol and the protocol under which the behavior card can suspend processing via the STOPPED signal. The present invention addresses these problems and deficiencies and others in the manner described below.
The present invention relates to a hardware design emulation system that includes an emulator or emulator/accelerator and one or more run-time assist units (RTAUs) that may include (but are not limited to) the behavior cards described in above-described U.S. Pat. No. 5,946,472. The emulator/accelerator executes a logic model that reflects a combination of a user model logic portion and a non-user-model logic portion
In one aspect, the invention further includes a handshaking controller that produces a domain step signal and a model step signal. The domain step signal indicates that the emulator is entering a state in which it is executing the next step of its emulation cycle. The domain step may or may not advance the user model. For example, the user model may not advance if the next step is merely communicating data with the host workstation or performing some other task defined by the non-user-model logic portion of the logic model. The model step signal indicates that the emulator is entering a state in which it is advancing the user model executing on the emulator/accelerator and associated RTAU(s).
Various types of RTAUs can be included. Such RTAUs can respond to combinations of the domain step signal and model step signal in different ways, thereby enhancing versatility in terms of the types of RTAUs that can be included in the system, especially as used in combination with one another in the same emulation. The behavior card described in U.S. Pat. No. 5,946,472 is an example of one type of RTAU. It includes a processor on which a user model program executes. Another type of RTAU is a network-based direct attach stimulus (NDAS) card, which moves data directly between the emulator and the workstation.
Depending upon the type of RTAU, it can respond to either the domain step signal, the model step signal or both. For example, a behavior card of the type described in the above-referenced patent does not distinguish between domain step signals and model step signals; it cant be programmed to respond to one, the other, or either signal. Each time the handshaking controller asserts the appropriate step signal, the behavior card advances the user model by performing the requisite processing in accordance with the next step of its programming. To indicate that it has begun such processing, it asserts an appropriate halt signal. Thus, it asserts a domain halt signal in response to the domain step signal, and asserts a model halt signal in response to the model step signal. When it has completed its processing, it deasserts the appropriate halt signal to indicate such completion.
In contrast, an NDAS card operates in response to both the domain step signal and the model step signal. In typical operation, when the handshaking controller asserts the domain step and model step signals, the NDAS card responds by asserting the domain and model halt signals and beginning a transfer of data. When it has completed the initial data transfer it deasserts the domain halt signal but may keep the model halt signal asserted if more data is to be transferred. The handshaking controller then reasserts the domain step signal, and the NDAS card responds by reasserting the domain halt signal; with each such domain step/halt handshake, the NDAS card transfers more data. When the NDAS card has no more data to transfer, it can deassert the model halt signal. Still other types of RTAUs can respond to combinations of the domain and model step signals in other ways, thereby providing an extremely versatile interface.
In accordance with another aspect of the invention, a RTAU may include a programmable counter circuit that causes it to skip steps. In other words, the counter can be programmed so that the RTAU does not assert the halt signal in response to every step signal; rather, the RTAU can assert the halt signal in response to every nth step signal. For example, the RTAU may respond to every other assertion of the step signal or every third assertion of the step signal, and so forth. This feature is useful in instances in which the emulated model is known to produce a usable output only every nth model step or every nth domain step.
In another aspect, the invention further includes signals that indicate to the RTAUs when another RTAU has suspended execution. Any of the RTAUs produces an output signal to indicate it has suspended execution. Each RTAU receives a xe2x80x9cSignal_Anyxe2x80x9d signal indicating that another RTAU asserted its output signal and a xe2x80x9cSignal_Allxe2x80x9d signal indicating that all of the RTAUs asserted their output signals. Each RTAU asserts its output signal in response to detecting assertion of the xe2x80x9cSignal_Anyxe2x80x9d signal. An OR-based logic network combines the output signals produced by the RTAUs to form xe2x80x9cSignal_Any.xe2x80x9d An AND-based logic network combines the output signals produced by the RTAUs to form xe2x80x9cSignal_All.xe2x80x9d
The emulators may be connected together to a central unit, referred to as a master panel, that provides interconnections for the emulator/accelerator boards, RTAUs, host workstation and other devices. The step generation circuitry and logic network for the xe2x80x9cSignal Anyxe2x80x9d and xe2x80x9cSignal_Allxe2x80x9d signals may be included in the master panel logic. In another aspect of the invention, multiple master panels may be cascaded together to form a global master panel that accommodates many more emulator/accelerators and RTAUs than a single master panel. Although each master panel includes the step generation circuitry, only that of one of the master panels, referred to as the primary master panel, is actively used in the global master panel configuration; the step generation circuitry of the other, cascaded or secondary master panels is bypassed and inactive. Each secondary master panel has splitter circuitry that splits or distributes the step signals it receives from the primary master panel or from another secondary master panel between it and the primary master panel. Each secondary master panel also has combiner circuitry that combines the halt signals it receives from the RTAUS or from another secondary master between it and the RTAUs. At least from the perspective of a single user""s emulation, the RTAUs associated with that emulation are connected to the last level of secondary master panels and are not connected to the primary master panel or to intermediate levels of secondary master panels.
The foregoing, together with other features and advantages of the present invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.